The present invention relates to the field of integrated circuit interconnection technology. More specifically, the present invention provides a static, nonvolatile programmable interconnect junction.
Interconnect is a fundamental component of integrated circuits. Interconnect is used to couple the elements, components, circuits, and signals in an electronic system together in order to perform functions. For example, interconnect is used to supply power to the electronic components. Interconnect is also used to implement analog and digital functions in electronic systems. Interconnect, especially programmable or configurable interconnect, is especially useful in particular applications, such as, but not limited to, programmable logic devices (PLDs) where it is desirable for interconnections to be programmably determined. Other applications may include microprocessors, memories, and application specific integrated circuits (ASICs), to name a few.
PLDs are well known to those in the electronic art. Programmable logic devices are commonly referred to as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs, PLDs, EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic.TM., and MAX.RTM. 5000, MAX.RTM. 7000, and FLEX.RTM. 8000 EPLDs made by Altera Corp.
PLDs are generally known in which many logic array blocks (LABs) are provided in a two-dimensional array. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR. The functions within LABs and LEs may be implemented using function generators, look-up tables, AND-OR arrays, product terms, multiplexers, and a multitude of other techniques. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs and LEs.
The configuration information of the LABs, LEs, and interconnections between these logical elements have been typically stored in memory cells. Memory cells may be used to programmably control the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.
Many different memory cell technologies may be used including dynamic random access memory (DRAM), static random access memory (SRAM), erasable-programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), Flash EEPROM memory, and antifuse, among others. Typically, the technology used to store the configuration information of the PLD should be compact, power efficient, programmable and nonvolatile, require little additional programming circuitry overhead, and generally provide enhancements to the performance and features of PLD logic modules and interconnections.
While PLDs have met with substantial success, such devices also meet with certain limitations. There is a continuing need for programmable logic integrated circuits with greater capacity, density, functionality, and performance. Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as "chips"), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. As the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for programmably interconnecting the elements and routing signals between the logic blocks. Also as PLDs increase in size and complexity, greater numbers of memory cells are required to hold the configuration information of the logical elements and many programmable interconnections are needed.
This produces a need to implement logic functions more efficiently and to improve the portion of the device which is devoted to interconnecting individual logic modules. The provision of additional or alternative techniques for implementing the programmable interconnection between the logic modules should have benefits sufficient to justify the additional circuitry and programming complexity. The capacity, complexity, and performance of PLDs are determined in a large part by the techniques used to implement the logic elements and interconnections. The techniques used to implement the logic and programmable interconnect should have improved operating characteristics such as lower power consumption, nonvolatility, greater device longevity, improved data retention, better transient performance, and superior voltage and current attributes, as well as many other characteristics. Furthermore, the technology should facilitate manufacturability and testability.
As can be seen, improved techniques for implementing programmable interconnect are needed, especially for implementing the logic and interconnects in a programmable integrated circuit.